The invention relates to a gate circuit including an N-channel and a P-channel insulated-gate field-effect transistor, whose parallel-connected drain-source paths constitute an analog signal gate, and a control circuit connected to the respective gate electrodes to turn on and/or turn off the two field-effect transistors. Gate circuits of this type are known per se and are employed, for example, as analog semiconductor switches in multiplexers.
As a result of the reduction of the effective channel length of present insulated-gate field-effect transistors, generally referred to as MOS (Metal Oxide Silicon) transistors, and the trend towards standard power-supply voltages, the electric field strength in MOS transistors has increased. When the strength of the electric field near the drain region of a MOS transistor has a value larger than 2 to 3.10.sup.5 V/cm this region will contain many high-energy electrons and holes. As a result of their high velocity these charge carriers collide with the atoms of the semiconductor material, so that charge carriers are scattered in all directions. These scattered charge carriers partly reach the gate oxide, in which they may be slowed down to such an extent that they remain therein as fixed charges.
Said fixed charges inter alia give rise to a change in threshold voltage of the MOS transistor. Depending on the amount of fixed charge there may be a considerable shift in threshold voltage, as a result of which the characteristics of the MOS transistor will be too far out of specification and its reliability will be reduced. In practice, a change in threshold voltage of a MOS transistor by more than 100 mV is generally not acceptable.
In BIMOS technology, in which both bipolar components and field-effect transistors are formed in the semiconductor substrate, the maximum permissible drain-source voltage in the conductive state is considered to be approximately 5.5 V for an N-channel MOS transistor and approximately 8.5 V for a P-channel MOS transistor, in order to ensure that the threshold voltage will not vary by more than 100 mV during the life of the relevant field-effect transistors. The higher permissible drain-source voltage for a P-channel MOS transistor is caused by the fact that in a P-channel MOS transistor the free charge carriers are mainly holes, which have a lower mobility than electrons, i.e. the holes experience a lower acceleration at the same field strength. In the nonconductive state the maximum permissible drain-source voltages are substantially higher and are mainly considered by breakdown of the parasitic diodes and the gate oxide of the transistors.
In English technical literature the above effect is referred to as the "hot-carrier effect". As a result of this, a gate circuit constructed by means of field-effect transistors in BIMOS technology can handle only signals having an r.m.s. value smaller than approximately 1.75 V if no additional steps are taken. Larger signals have to be attenuated before they can be applied to the signal gate. However, this results in an undesired deterioration of the signal-to-noise ratio, because the signal strength is reduced and the noise increases as a result of the noise contributed by the attenuator.